1. Field of the Invention
The present invention relates to a data selection circuit that outputs a data selection signal to a functional circuit having a data selection pulse input terminal, and a data transmission circuit, a ramp wave generation circuit and a solid-state imaging device using the data selection circuit.
This application claims priority to and the benefits of Japanese Patent Application No. 2010-119480 filed on May 25, 2010, the disclosure of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 14 illustrates a configuration example of a solid-state imaging device in which an analog-to-digital converter (ADC) is mounted for each pixel row.
A solid-state imaging device 1 illustrated in FIG. 14 includes an imaging section 2, a row scanning circuit 3, a column scanning circuit 4, a timing control circuit 5, an ADC group 6, a ramp wave generation circuit 7, a counter 8, and a data output circuit 9. The data output circuit 9 includes a sense amplifier circuit.
The imaging section 2 includes a photodiode and an amplifier inside a pixel. Unit pixels 20 that output pixel signals in response to the intensity or the quantity of an incident electromagnetic wave are arranged in the form of a matrix in the imaging section 2. The timing control circuit 5 is a control circuit for sequentially reading the pixel signals from the imaging section 2 and generates an internal clock. The row scanning circuit 3 controls row addressing or row scanning of the imaging section 2 via a row control line 11. The column scanning circuit 4 controls column addressing or column scanning of the ADC group 6. The ramp wave generation circuit 7 generates a ramp wave whose voltage value changes in a staircase pattern.
The ADC group 6 has an n-bit digital signal conversion function and includes a row ADC section 60 that is installed for each vertical signal line 13 corresponding to each pixel row. The row ADC section 60 includes a comparator 601 and a latch section 602. The comparator 601 compares the ramp wave generated by the ramp wave generation circuit 7 with an analog signal obtained through each vertical signal line 13 from the unit pixel 20 for each row control signal 11. The latch section 602 includes latch circuits 603 and 604 that retain a counting result of the counter 8 that counts a comparison time. Output of each latch section 602 is connected to a 2n-bit width horizontal transmission line 117. The data output circuit 9 includes 2n sense circuits that correspond to the horizontal lines 117, respectively.
Next, an operation of the solid-state imaging device 1 will be described. In a first read operation, a reset level including noise of the pixel signal is read from each unit pixel 20 of a selected row of the imaging section 2 as an analog pixel signal, and thereafter, in a second read operation, a signal level is read. The reset level and the signal level are input to the ADC group 6 through the vertical signal line 13 according to a time sequence.
After first reading from the unit pixel 20 of an arbitrary row to the vertical signal line 13 is stabilized, the ramp wave of the staircase pattern whose reference voltage has been temporally changed is generated by the ramp wave generation circuit 7 and input to the comparator 601. The comparator 601 compares a voltage of the arbitrary vertical signal line 13 with the ramp wave.
In parallel with the input of the ramp wave to the comparator 601, first counting is performed by the counter 8.
When the voltage level of the ramp wave is equal to the voltage of the arbitrary vertical signal line 13, an output of the comparator 601 is inverted, and at the same time, the counting value according to the comparison time period is retained in the latch unit 602. At the time of first reading, since a variation in the reset level of the unit pixel 20 is usually small and the reset voltage is common in all pixels, the output of the arbitrary vertical line 13 is approximately equal to a known value. Thus, at the time of first reset level reading, the comparison time period can be reduced by appropriately adjusting the voltage of the ramp wave.
At the time of second reading, in addition to the reset level, the signal level corresponding to an incident light amount of each unit pixel 20 is read, and the same operation as in the first reading is performed. That is, after second reading from the unit pixel 20 of an arbitrary row to the arbitrary vertical signal line 13 is stabilized, the ramp wave of the staircase pattern whose reference voltage has been temporally changed is generated by the ramp wave generation circuit 7 and input to the comparator 601. The comparator 601 compares a voltage of the arbitrary vertical signal line 13 with the ramp wave. In parallel with the input of the ramp wave to the comparator 601, second counting is performed by the counter 8.
When the voltage level of the ramp wave is equal to the voltage of the arbitrary vertical signal line 13, an output of the comparator 601 is inverted, and at the same time, the count value according to the comparison time period is retained in the latch section 602. The first counting value is retained, for example, in the latch circuit 603, and the second counting value is retained, for example, in the latch circuit 604.
After the two reading operations are finished, a first n-bit digital signal and a second n-bit digital signal retained in the latch section 602 are output via the 2n vertical transmission lines 117 and detected at the digital output circuit 9 by the column scanning circuit 4. Subsequently, in a subtraction circuit, after the signal obtained by the first reading is sequentially subtracted from the signal obtained by the second reading, the subtracted signal is output to the outside. Thereafter, the same operation is sequentially repeated for each row, and a two-dimensional image is generated.
Japanese Unexamined Patent Application, First Publication No. 2002-158933 discloses a scanning circuit that can be applied to a solid-state imaging device.